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Thursday, August 26, 2010

THE IC 7400 SERIES

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The following is a list of 7400 series digital logic integrated circuits. The SN7400 series originated with TTL integrated circuits made by Texas Instruments. Because of the popularity of these parts, they were second-sourced by other manufacturers who kept the 7400 sequence number as an aid to identification of compatible parts. As well, compatible TTL parts originated by other manufacturers were second sourced in the TI product line under a 74xxx series part number.










Just the base numbers are listed below, that is: parts are listed here as if made in the basic, standard power and speed, TTL form, although many later parts were never manufactured with that technology.










7400: Quad 2-input NAND gate




7401: Quad 2-input NAND gate with open collector outputs




7402: Quad 2-input NOR gate




7403: Quad 2-input NAND gate with open collector outputs (different pinout than 7401)




7404: Hex Inverter




7405: Hex Inverter with open collector outputs




7406: Hex Inverter Buffer/Driver with 30V open collector outputs




7407: Hex Buffer/Driver with 30V open collector outputs




7408: Quad 2-input AND gate




7409: Quad 2-input AND gate with open collector outputs




7410: Triple 3-input NAND gate




7411: Triple 3-input AND gate




7412: Triple 3-input NAND gate with open collector outputs




7413: Dual Schmitt trigger 4-input NAND gate




7414: Hex Schmitt trigger Inverter




7415: Triple 3-input AND gate with open collector outputs




7416: Hex Inverter Buffer/Driver with 15V open collector outputs




7417: Hex Buffer/Driver with 15V open collector outputs




7418: Dual 4-input NAND gate with schmitt trigger inputs




7419: Hex Schmitt trigger Inverter




7420: Dual 4-input NAND gate




7421: Dual 4-input AND gate




7422: Dual 4-Input NAND gate with open collector outputs




7423: Expandable Dual 4-input NOR gate with strobe




7424: Quad 2-input NAND gate gates with Schmitt-trigger line-receiver inputs.




7425: Dual 4-input NOR gate with Strobe




7426: Quad 2-input NAND gate with 15V open collector outputs




7427: Triple 3-input NOR gate




7428: Quad 2-input NOR Buffer




7430: 8-input NAND gate




7431: Hex Delay Elements




7432: Quad 2-input OR gate




7433: Quad 2-input NOR Buffer with open collector outputs




7436: Quad 2-input NOR Gate (different pinout than 7402)




7437: Quad 2-input NAND Buffer




7438: Quad 2-input NAND Buffer with open collector outputs




7439: Quad 2-input NAND Buffer




7440: Dual 4-input NAND Buffer




7441: Binary-coded decimal to Decimal Decoder/Nixie tube Driver




7442: BCD to Decimal Decoder




7443: Excess-3 to Decimal Decoder




7444: Excess-3-Gray code to Decimal Decoder




7445: BCD to Decimal Decoder/Driver




7446: BCD to Seven-segment display Decoder/Driver with 30V open collector outputs




7447: BCD to 7-segment Decoder/Driver with 15V open collector outputs




7448: BCD to 7-segment Decoder/Driver with Internal Pullups




7449: BCD to 7-segment Decoder/Driver with open collector outputs




7450: Dual 2-Wide 2-input AND-OR-Invert Gate (one gate expandable)




7451: Dual 2-Wide 2-Input AND-OR-Invert Gate




7452: Expandable 4-Wide 2-input AND-OR Gate




7453: Expandable 4-Wide 2-input AND-OR-Invert Gate




7454: 4-Wide 2-Input AND-OR-Invert Gate




7455: 2-Wide 4-Input AND-OR-Invert Gate (74H version is expandable)




7456: 50:1 Frequency divider




7457: 60:1 Frequency divider




7458: 2-Input & 3-Input AND-OR Gate




7459: 2-Input & 3-Input AND-OR-Invert Gate




7460: Dual 4-input Expander




7461: Triple 3-input Expander




7462: 3-2-2-3-Input AND-OR Expander




7463: Hex Current Sensing Interface Gates




7464: 4-2-3-2-Input AND-OR-Invert Gate




7465: 4-2-3-2 Input AND-OR-Invert Gate with open collector output




7468: Dual 4 Bit Decade Counters




7469: Dual 4 Bit Binary Counters




7470: AND-Gated Positive Edge Triggered J-K Flip-Flop with Preset and Clear




74H71: AND-OR-Gated J-K Master-Slave Flip-Flop with Preset




74L71: AND-Gated R-S Master-Slave Flip-Flop with Preset and Clear




7472: AND Gated J-K Master-Slave Flip-Flop with Preset and Clear




7473: Dual J-K Flip-Flop with Clear




7474: Dual D Positive Edge Triggered Flip-Flop with Preset and Clear




7475: 4-bit Bistable Latch




7476: Dual J-K Flip-Flop with Preset and Clear




7477: 4-bit Bistable Latch




74H78, 74L78: Dual J-K Flip-Flop with Preset, Common Clear, and Common Clock




74LS78A: Dual Negative Edge Triggered J-K Flip-Flop with Preset, Common Clear, and Common Clock




7479: Dual D Flip-Flop




7480: Gated Full Adder




7481: 16-bit Random Access Memory




7482: 2-bit Binary Full Adder




7483: 4-bit Binary Full Adder




7484: 16-bit Random Access Memory




7485: 4-bit Magnitude Comparator




7486: Quad 2-input XOR gate




7487: 4-bit True/Complement/Zero/One Element




7488: 256-bit Read-only memory




7489: 64-bit Random Access Memory




7490: Decade Counter (separate Divide-by-2 and Divide-by-5 sections)




7491: 8-bit Shift Register, Serial In, Serial Out, Gated Input




7492: Divide-by-12 Counter (separate Divide-by-2 and Divide-by-6 sections)




7493: 4-bit Binary Counter (separate Divide-by-2 and Divide-by-8 sections)




7494: 4-bit Shift register, Dual Asynchronous Presets




7495: 4-bit Shift register, Parallel In, Parallel Out, Serial Input




7496: 5-bit Parallel-In/Parallel-Out Shift register, Asynchronous Preset




7497: Synchronous 6-bit Binary Rate Multiplier




7498: 4-bit Data Selector/Storage Register




7499: 4-bit Bidirectional Universal Shift register




74100: Dual 4-Bit Bistable Latch




74101: AND-OR-Gated J-K Negative-Edge-Triggered Flip-Flop with Preset




74102: AND-Gated J-K Negative-Edge-Triggered Flip-Flop with Preset and Clear




74103: Dual J-K Negative-Edge-Triggered Flip-Flop with Clear




74104: J-K Master-Slave Flip-Flop




74105: J-K Master-Slave Flip-Flop




74106: Dual J-K Negative-Edge-Triggered Flip-Flop with Preset and Clear




74107: Dual J-K Flip-Flop with Clear




74107A: Dual J-K Negative-Edge-Triggered Flip-Flop with Clear




74108: Dual J-K Negative-Edge-Triggered Flip-Flop with Preset, Common Clear, and Common Clock




74109: Dual J-Not-K Positive-Edge-Triggered Flip-Flop with Clear and Preset




74110: AND-Gated J-K Master-Slave Flip-Flop with Data Lockout




74111: Dual J-K Master-Slave Flip-Flop with Data Lockout




74112: Dual J-K Negative-Edge-Triggered Flip-Flop with Clear and Preset




74113: Dual J-K Negative-Edge-Triggered Flip-Flop with Preset




74114: Dual J-K Negative-Edge-Triggered Flip-Flop with Preset, Common Clock and Clear




74116: Dual 4-bit Latches with Clear




74118: Hex Set/Reset Latch




74119: Hex Set/Reset Latch




74120: Dual Pulse Synchronizer/Drivers




74121: Monostable Multivibrator




74122: Retriggerable Monostable Multivibrator with Clear




74123: Dual Retriggerable Monostable Multivibrator with Clear




74124: Dual Voltage-Controlled Oscillator




74125: Quad Bus Buffer with Three-State Outputs, Negative Enable




74126: Quad Bus Buffer with Three-state Outputs, Positive Enable




74128: Quad 2-input NOR Line Driver




74130: Quad 2-input AND gate Buffer with 30V open collector outputs




74131: Quad 2-input AND gate Buffer with 15V open collector outputs




74132: Quad 2-input NAND Schmitt trigger




74133: 13-Input NAND gate




74134: 12-Input NAND gate with Three-state Output




74135: Quad Exclusive-OR/NOR Gate




74136: Quad 2-Input XOR gate with open collector outputs




74137: 3 to 8-line Decoder/Demultiplexer with Address Latch




74138: 3 to 8-line Decoder/Demultiplexer




74139: Dual 2 to 4-line Decoder/Demultiplexer




74140: Dual 4-input NAND Line Driver




74141: BCD to Decimal Decoder/Driver for cold-cathode indicator/NIXIE Tube




74142: Decade Counter/Latch/Decoder/Driver for Nixie Tubes




74143: Decade Counter/Latch/Decoder/7-segment Driver, 15 mA Constant Current




74144: Decade Counter/Latch/Decoder/7-segment Driver, 15V open collector outputs




74145: BCD to Decimal Decoder/Driver




74147: 10-Line to 4-Line Priority Encoder




74148: 8-Line to 3-Line Priority Encoder




74150: 16-Line to 1-Line Data Selector/Multiplexer




74151: 8-Line to 1-Line Data Selector/Multiplexer




74152: 8-Line to 1-Line Data Selector/Multiplexer




74153: Dual 4-Line to 1-Line Data Selector/Multiplexer




74154: 4-Line to 16-Line Decoder/Demultiplexer




74155: Dual 2-Line to 4-Line Decoder/Demultiplexer




74156: Dual 2-Line to 4-Line Decoder/Demultiplexer with open collector outputs




74157: Quad 2-Line to 1-Line Data Selector/Multiplexer, Noninverting




74158: Quad 2-Line to 1-Line Data Selector/Multiplexer, Inverting




74159: 4-Line to 16-Line Decoder/Demultiplexer with open collector outputs




74160: Synchronous 4-bit Decade Counter with Asynchronous Clear




74161: Synchronous 4-bit Binary Counter with Asynchronous Clear




74162: Synchronous 4-bit Decade Counter with Synchronous Clear




74163: Synchronous 4-bit Binary Counter with Synchronous Clear




74164: 8-bit Parallel-Out Serial Shift Register with Asynchronous Clear




74165: 8-bit Serial Shift Register, Parallel Load, Complementary Outputs




74166: Parallel-Load 8-Bit Shift Register




74167: Synchronous Decade Rate Multiplier




74168: Synchronous 4-Bit Up/Down Decade Counter




74169: Synchronous 4-Bit Up/Down Binary Counter




74170: 4 by 4 Register File with open collector outputs




74172: 16-Bit Multiple Port Register File with Three-state Outputs




74173: Quad D Flip-Flop with Three-state Outputs




74174: Hex D Flip-Flop with Common Clear




74175: Quad D Edge-Triggered Flip-Flop with Complementary Outputs and Asynchronous Clear




74176: Presettable Decade (Bi-Quinary) Counter/Latch




74177: Presettable Binary Counter/Latch




74178: 4-bit Parallel-Access Shift Register




74179: 4-bit Parallel-Access Shift Register with Asynchronous Clear and Complementary QD Outputs




74180: 9-bit Odd/Even Parity bit Generator and Checker




74181: 4-bit Arithmetic Logic Unit and Function Generator




74182: Lookahead Carry Generator




74183: Dual Carry-Save Full adder




74184: BCD to Binary Converter




74185: Binary to BCD Converter




74186: 512-bit (64x8) Read-only memory with open collector outputs




74187: 1024-bit (256x4) Read only memory with open collector outputs




74188: 256-bit (32x8) Programmable read-only memory with open collector outputs




74189: 64-bit (16x4) RAM with Inverting three-state Outputs




74190: Synchronous Up/Down Decade Counter




74191: Synchronous Up/Down Binary Counter




74192: Synchronous Up/Down Decade Counter with Clear




74193: Synchronous Up/Down Binary Counter with Clear




74194: 4-bit Bidirectional Universal Shift Register




74195: 4-bit Parallel-Access Shift Register




74196: Presettable Decade Counter/Latch




74197: Presettable Binary Counter/Latch




74198: 8-bit Bidirectional Universal Shift Register




74199: 8-bit Bidirectional Universal Shift Register with J-Not-K Serial Inputs




74200: 256-bit RAM with Three-state Outputs




74201: 256-bit (256x1) RAM with three-state outputs




74206: 256-bit RAM with open collector outputs




74209: 1024-bit (1024x1) RAM with three-state output




74210: Octal Buffer




74219: 64-bit (16x4) RAM with Noninverting three-state outputs




74221: Dual Monostable Multivibrator with Schmitt trigger input




74222: 16 by 4 Synchronous FIFO Memory with three-state outputs




74224: 16 by 4 Synchronous FIFO Memory with three-state outputs




74225: Asynchronous 16x5 FIFO Memory




74226: 4-bit Parallel Latched Bus Transceiver with three-state outputs




74230: Octal Buffer/Driver with three-state outputs




74232: Quad NOR Schmitt trigger




74237: 1-of-8 Decoder/Demultiplexer with Address Latch, Active High Outputs




74238: 1-of-8 Decoder/Demultiplexer, Active High Outputs




74239: Dual 2-of-4 Decoder/Demultiplexer, Active High Outputs




74240: Octal Buffer with Inverted three-state outputs




74241: Octal Buffer with Noninverted three-state outputs




74242: Quad Bus Transceiver with Inverted three-state outputs




74243: Quad Bus Transceiver with Noninverted three-state outputs




74244: Octal Buffer with Noninverted three-state outputs




74245: Octal Bus Transceiver with Noninverted three-state outputs




74246: BCD to 7-segment Decoder/Driver with 30V open collector outputs




74247: BCD to 7-segment Decoder/Driver with 15V open collector outputs




74248: BCD to 7-segment Decoder/Driver with Internal Pull-up Outputs




74249: BCD to 7-segment Decoder/Driver with open collector outputs




74251: 8-line to 1-line Data Selector/Multiplexer with complementary three-state outputs




74253: Dual 4-line to 1-line Data Selector/Multiplexer with three-state outputs




74255: Dual 4-bit Addressable Latch




74256: Dual 4-bit Addressable Latch




74257: Quad 2-line to 1-line Data Selector/Multiplexer with Noninverted three-state outputs




74258: Quad 2-line to 1-line Data Selector/Multiplexer with Inverted three-state outputs




74259: 8-bit Addressable Latch




74260: Dual 5-Input NOR Gate




74261: 2-bit by 4-bit Parallel Binary Multiplier




74265: Quad Complementary Output Elements




74266: Quad 2-Input XNOR gate with open collectorOutputs




74270: 2048-bit (512x4) Read Only Memory with open collector outputs




74271: 2048-bit (256x8) Read Only Memory with open collector outputs




74273: 8-bit Register with Reset




74274: 4-bit by 4-bit Binary Multiplier




74275: 7-bit Slice Wallace tree




74276: Quad J-Not-K Edge-Triggered Flip-Flops with Separate Clocks, Common Preset and Clear




74278: 4-bit Cascadeable Priority Registers with Latched Data Inputs




74279: Quad Set-Reset Latch




74280: 9-bit Odd/Even Parity bit Generator/Checker




74281: 4-bit Parallel Binary Accumulator




74283: 4-bit Binary Full adder




74284: 4-bit by 4-bit Parallel Binary Multiplier (low order 4 bits of product)




74285: 4-bit by 4-bit Parallel Binary Multiplier (high order 4 bits of product)




74287: 1024-bit (256x4) Programmable read-only memory with three-state outputs




74288: 256-bit (32x8) Programmable read-only memory with three-state outputs




Half adder



A half adder is a logical circuit that performs an addition operation on two one-bit binary numbers often written as A and B. The half adder output is a sum of the two inputs usually represented with the signals Cout and S where . Following is the logic table for a half adder:






Inputs Outputs


A B C S


0 0 0 0


0 1 0 1


1 0 0 1


1 1 1 0










Example half adder circuit diagramAs an example, a Half Adder can be built with an XOR gate and an AND gate.






___________


A ------








Half
-----




Adder








-----


B ------
___________




[edit] Full adder






Schematic symbol for a 1-bit full adder with Cin and Cout drawn on sides of block to emphasize their use in a multi-bit adder.A full adder is a logical circuit that performs an addition operation on three one-bit binary numbers often written as A, B, and Cin. The full adder produces a two-bit output sum typically represented with the signals Cout and S where . The full adder's truth table is:






Inputs Outputs


A B Ci Co S


0 0 0 0 0


1 0 0 0 1


0 1 0 0 1


1 1 0 1 0


0 0 1 0 1


1 0 1 1 0


0 1 1 1 0


1 1 1 1 1






A full adder can be implemented in many different ways such as with a custom transistor-level circuit or composed of other gates. One example implementation is with and .










Example full adder circuit diagram


Inputs: {A, B, Cin} → Outputs: {S, Cout}File:Full Adder.JPG


Example full adder circuit diagram using only NAND and XOR gates


Inputs: {A, B, Cin} → Outputs: {S, Cout}In this implementation, the final OR gate before the carry-out output may be replaced by an XOR gate without altering the resulting logic. Using only two types of gates is convenient if the circuit is being implemented using simple IC chips which contain only one gate type per chip.






A full adder can be constructed from two half adders by connecting A and B to the input of one half adder, connecting the sum from that to an input to the second adder, connecting Ci to the other input and OR the two carry outputs. Equivalently, S could be made the three-bit XOR of A, B, and Ci, and Co could be made the three-bit majority function of A, B, and Ci.






[edit] Multiple-bit adders


[edit] Ripple carry adder


It is possible to create a logical circuit using multiple full adders to add N-bit numbers. Each full adder inputs a Cin, which is the Cout of the previous adder. This kind of adder is a ripple carry adder, since each carry bit "ripples" to the next full adder. Note that the first (and only the first) full adder may be replaced by a half adder.






The layout of ripple carry adder is simple, which allows for fast design time; however, the ripple carry adder is relatively slow, since each full adder must wait for the carry bit to be calculated from the previous full adder. The gate delay can easily be calculated by inspection of the full adder circuit. Each full adder requires three levels of logic. In a 32-bit [ripple carry] adder, there are 32 full adders, so the critical path (worst case) delay is 31 * 2(for carry propagation) + 3(for sum) = 65 gate delays.






[edit] Carry look-ahead adders


Main article: Carry look-ahead adder


To reduce the computation time, engineers devised faster ways to add two binary numbers by using carry lookahead adders. They work by creating two signals (P and G) for each bit position, based on whether a carry is propagated through from a less significant bit position (at least one input is a '1'), a carry is generated in that bit position (both inputs are '1'), or if a carry is killed in that bit position (both inputs are '0'). In most cases, P is simply the sum output of a half-adder and G is the carry output of the same adder. After P and G are generated the carries for every bit position are created. Some advanced carry look ahead architectures are the Manchester carry chain, Brent-Kung adder, and the Kogge-Stone adder.










4-bit adder with Carry Look AheadFile:Four bit ripple carry adder circuit diagram.png


4-bit adder with logic gates shownSome other multi-bit adder architectures break the adder into blocks. It is possible to vary the length of these blocks based on the propagation delay of the circuits to optimize computation time. These block based adders include the carry bypass adder which will determine P and G values for each block rather than each bit, and the carry select adder which pre-generates sum and carry values for either possible carry input to the block.






Other adder designs include the conditional sum adder, carry skip adder, and carry complete adder.






[edit] Lookahead Carry Unit


Main article: Lookahead Carry Unit


By combining multiple carry look-ahead adders even larger adders can be created. This can be used at multiple levels to make even larger adders. For example, the following adder is a 64-bit adder that uses four 16-bit CLAs with two levels of LCUs.










A 64-bit adder[edit] 3:2 compressors


We can view a full adder as a 3:2 compressor: it sums three one-bit inputs, and returns the result as a single two-bit number. Thus, for example, an input of 101 results in an output of 1+0+1=10 (2). The carry-out represents bit one of the result, while the sum represents bit zero. Likewise, a half adder can be used as a 2:2 compressor.






3:2 compressors can be used to speed up the summation of three or more addends. If the addends are exactly three, the layout is known as the carry-save adder. If the addends are four or more, more than one layer of compressors is necessary and there are various possible design for the circuit: the most common are Dadda and Wallace trees. This kind of circuit is most notably used in multipliers, which is why these circuits are also known as Dadda and Wallace multipliers.